gate-lines efficiency

digital binary (bit) electronic hardware bases 2 and 4, oft equally effectual, aren't always most efficient for process

This example is the multiplexor realestate in gate-lines:

The 1-of-2^N multiplexor decodes N address bits in AND-gates, AND with the input bit, the one selected reaches the OR-stage and thence output. If we model gates simply, there are input- and output-lines, and the gate itself is tiny at the end of a line (and down in the practical substrate); ... but the stage delays cut the overall utilization efficiency: Whence a tally:

The general equation for approx. total realestate by base-radix R, (R/R-1)((L2 R)+2+(1/R)) 2^N, bottoms at (R-(Ln R) = 1+3Ln2), base R = 4.607; total = 5.647; relative efficiency cost = 2.562 (external lines).

[under revision for a simpler in-practice model]

The TTL (cf 7400-series) NORAND consisted of AND-structure reverse-diode inputs to a transistor amplifier, which output OR-structure summed into the final amplifier, which had an inverting NOT-structure output. And most other gates in the entire line consisted of one or more layers of NORANDs, eg. the AND-gate was a multiinput single-AND single second-level NOR with an additional NORAND tied-down as a NOT-output ... (so reminiscent of the ten-transistor imported radio of the 1960's: that had three transistors actually connected and the third was tied-down as a diode) ... the TTL NAND was therefore slower by that one extra NOT stage.

The multiplexor, was a significant high-tech use of the NORAND: it fully decoded address bits; which required its AND-structure, and needed only one output answer, which was the OR-sum of all the ANDs -only one selected per address-... its NOT-output being a choice.

Decoding the addresses, took 2 NORANDs per address bit, buffering the positive input and generating a NOT-version (they usually did not change the TTL staging structure inside: that came later in LSI, large scale integration, and generated Industry Alerts when all the outputs twitched and drifted, despite its spec'd. power-ground-EMI caps. and changed signal-set-up- and -fanout-timings); and an AND-structure for each of 2^N unique addresses, including its data bit; and the NOR-structure output. The data input AND-structure input for each of bits for any base, plus the base-number of bits to decode the unique address; then a tree of condensing stages for multiplexing large numbers of input bits, which stages took additional time-per, which factors-down the hardward efficiency (cf large numbers of slow processors, are nominally equivalent to fewer faster processors if the work is general and not special-case required instantly):

Many attempts were made to make TTL more substrate-efficient: the "no-gain trick" allowed adjacent inputs fairly closely spaced, without (NNN)PN- or (PPP)NP-crossleak, while fast draining any floating charge: one of the major slowdowns in TTL. Schottky itself reduced excess base (over)drive-charge by drawing-off through a low-voltage Schottky diode into the collector. Low-power Schottky balanced TTL-similar speed at lower total power usage; which also allowed for higher density LSI. Later follow-ons, Integrated Injection Logic I2L, and Advanced CMOS-inside-TTL ACT, and Advanced cmos-inside-Schottky-TTL AST attempted to further reduce power and increase speed ... these were commonly used in V-LSI where internal speed was valued. And soon thereafter, VHDL and computer-on-a-chip dominated the industry allotment for new-research, virtually squelching TTL advances.

[under construction]

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